Single Bit and Multi-Bit Flash Memory Cells
Flash memory devices have been known for many years. Typically, each memory cell within a flash memory device stores one bit of information. The traditional way to store a bit in a flash memory cell has been by supporting two states of the memory cell. One state represents a logical “0” and the other state represents a logical “1”.
In a flash memory cell, the two states are implemented by having a floating gate situated above the cell's channel (the area connecting the source and drain elements of the cell's transistor), and having two valid states for the amount of charge stored within the floating gate. Typically, one state is with zero charge in the floating gate and is the unwritten state of the cell after being erased (commonly defined to represent the “1” state) and the other state is with some amount of negative charge in the floating gate (commonly defined to represent the “0” state). Having negative charge in the gate causes the threshold voltage of the cell's transistor (i.e. the voltage that has to be applied to the transistor's control gate in order to cause the transistor to conduct) to increase. It is possible to read the stored bit by checking the threshold voltage of the cell. If the threshold voltage is in the higher state then the bit value is “0” and if the threshold voltage is in the lower state then the bit value is “1”. Actually there is no need to accurately read the cell's threshold voltage. All that is needed is to correctly identify in which of the two states the cell is currently located. For this purpose it is sufficient to compare the threshold voltage of the cell to a reference voltage that is between the two states, and to determine if the cell's threshold voltage is below or above the reference value.
FIG. 1A (prior art) shows graphically how this works. Specifically, FIG. 1A shows a distribution of the threshold voltages of a large population of cells. Because the cells in a flash device are not exactly identical in their characteristics and behavior (due to, for example, small variations in impurity concentrations or defects in the silicon structure), applying the same programming operation to all of the cells does not cause all of the cells to have exactly the same threshold voltage. Instead, the threshold voltage is distributed as shown in FIG. 1A. Cells storing a value of “1” typically have a negative threshold voltage, such that most of the cells have a threshold voltage close to the central voltage value of the left peak (labeled 1) of FIG. 1A, with fewer cells having threshold voltages lower or higher than the central voltage of the left peak. Similarly, cells storing a value of “0” typically have a positive threshold voltage, such that most of the cells have a threshold voltage close to the central voltage of the right peak (labeled 0) of FIG. 1A, with fewer cells having threshold voltages lower or higher than the central voltage of the right peak.
In recent years, a new kind of flash device has appeared on the market, using “Multi Level Cells” (MLC). The term “Multi-Level Cell” is misleading because flash memory with a single bit per cell uses multiple i.e. two levels, as described above. Therefore, the term “Single Bit Cell” (SBC) is used hereinafter to refer to a memory cell of two levels and the term “Multi-Bit Cell” (MBC) is used hereinafter to refer to a memory cell of more than two levels, i.e. more than one bit per cell. The most common MBC flash memories at present are ones with two bits per cell, and therefore examples are given below using such MBC memories. It should however be understood that the present invention is equally applicable to flash memory devices that support more than two bits per cell. A single MBC cell storing two bits of information is in one of four different states. As the cell's “state” is represented by the cell's threshold voltage, an MBC cell supports four different valid ranges for the cell's threshold voltage. FIG. 1B (prior art) shows the threshold voltage distribution for a typical MBC cell of two bits per cell. As expected, FIG. 1B has four peaks, each peak corresponding to one state. As for the SBC, each state is actually a voltage range and not a single voltage. When reading the cell's contents, the cell's threshold voltage must be correctly identified in a definite voltage range. For a prior art example of an MBC flash device see U.S. Pat. No. 5,434,825 to Harari that is included by reference for all purposes as if fully set forth herein.
A cell designed for MBC operation e.g. in four states is typically operable as an SBC cell with two states. For example, Conley et al. in U.S. Pat. No. 6,426,893 incorporated by reference for all purposes as if fully set forth herein, disclosed the use of both MBC and SBC modes within the same device, and selecting certain parts of the device to operate with highest density in MBC mode, while other parts are used in SBC mode to provide better performance.
MBC devices provide a significant cost advantage. An MBC device with two bits per cell requires about half the area of a silicon wafer than an SBC of similar capacity. However, there are drawbacks to using MBC flash. Average read and write times of MBC memories are longer than of SBC memories, resulting in worse performance. Also, the reliability of MBC is lower than SBC. The differences between the threshold voltage ranges in MBC are much smaller than in SBC. Thus, a disturbance in the threshold voltage (e.g leakage of stored charge causing a threshold voltage drift or interference from operating neighboring cells) that are insignificant in SBC because of the large gap between the two states, may cause an MBC cell to move from one state to another, resulting in an erroneous bit. The end result is a lower performance specification of MBC cells in terms of data retention time or the endurance of the device to many write/erase cycles.
NAND Flash Memory Devices
Flash memory devices are typically divided into NOR devices and NAND devices, the names being derived from the way the individual memory cells are interconnected within the cells array. NOR devices are random access—a host computer accessing a NOR flash device can provide the device any address on its address pins and immediately retrieve data stored in that address on the device's data pins. This is much like SRAM or EPROM memories operate. NAND devices, on the other hand, are not random access but serial access. It is not possible to access any random address in the way described above for NOR—instead the host has to write into the device a sequence of bytes which identifies both the type of the requested command (e.g. read, write, erase, etc.) and the address to be used for that command. The address identifies a page (the smallest chunk of flash memory that can we written in a single operation) or a block (the smallest chunk of flash memory that can be erased in a single operation), and not a single byte or word. It is true that the read and write command sequences contain addresses of single bytes or words, but in reality the NAND flash device always reads from the memory cells and writes to the memory cells complete pages. After a page of data is read from the array into a buffer inside the device, the host can access the data bytes or words one by one by serially clocking them out using a strobe signal.
Because of the non-random access of NAND devices, they cannot be used for running code directly from the flash memory. This is contrary to NOR devices which support direct code execution (typically called “eXecution In Place” or “XIP”). Therefore NOR devices are the ones typically used for code storage. However, NAND devices have advantages that make them very useful for data storage. NAND devices are cheaper than NOR devices of the same bit capacity, or equivalently—NAND devices provide many more bits of storage than NOR devices for the same cost. Also, the write and erase performance of NAND devices is much faster than of NOR devices. These advantages make the NAND flash memory technology the technology of choice for storing data.
NAND Interface Protocols
A typical SBC NAND device is Toshiba TC58NVG1S3B that provides 2 Gbit of storage. A typical MBC NAND device is Toshiba TC58NVG2D4B that provides 4 Gbit of storage. The data sheets of both devices are incorporated by reference for all purposes as if fully set forth herein.
As can be seen from the aforementioned data sheets, those two NAND devices have a similar interface. These NAND devices use the same electrical signals for coordinating commands and data transfer between the NAND flash device and a host device. Those signals include data lines and a few control signals—ALE (Address Latch Enable), CLE (Command Latch Enable), WE\ (Write Enable), and more. The SBC and MBC devices are not fully identical in their behavior—the time it takes to write an MBC page is much longer than time it takes to write an SBC page. However, the electrical signals used in both devices and their functionalities are the same. This type of interface protocol is known in the art as “NAND interface”. Even though the “NAND interface protocol” has not, to date, been formally standardized by a standardization body, the manufacturers of NAND flash devices all follow the same protocol for supporting the basic subset of NAND flash functionality. This is done so that customers using NAND devices within their electronic products could use NAND devices from any manufacturer without having to tailor their hardware or software for operating with the devices of a specific vendor. It is noted that even NAND vendors that provide extra functionality beyond this basic subset of functionality ensure that the basic functionality is provided in order to provide compatibility with the protocol used by the other vendors, at least to some extent.
In this application the term “NAND Interface protocol” (or “NAND interface” in short) means an interface protocol between an initiating device and a responding device that in general follows the protocol between a host device and a NAND flash device for the basic read, write and erase operations, even if it is not fully compatible with all timing parameters, not fully compatible with respect to other commands supported by NAND devices, or contains additional commands not supported by NAND devices. In other words, the term “NAND interface” refers to any interface protocol that uses sequences of transferred bytes equivalent in functionality to the sequences of bytes used when interfacing with the Toshiba TC58NVG1S3B NAND device for reading (opcode 00H), writing (opcode 80H) and erasing (opcode 60H), and also uses control signals equivalent in functionality to the CLE, ALE, CE, WE and RE signals of the above NAND device.
It is noted that the “NAND interface protocol” is not symmetric. Thus, it is always the host device which initiates the interaction over a NAND interface, and never the flash device.
A given device (e.g. a controller, flash device, host device, etc.) is said to comprise, include or have a “NAND interface” if the given device includes elements (e.g. hardware, software, firmware or any combination thereof) necessary for supporting the NAND interface protocol (e.g. for interacting with another device using a NAND interface protocol).
An interface (e.g. a NAND interface or an interface associated with another protocol) of a given device (e.g. a controller device) may be a “host-side interface” (e.g. the given device is adapted to interact with a host device using the host-side interface) or the interface of the given device may be a “flash memory device-side interface” (e.g. the given device is adapted to interact with a flash memory device using the flash memory device-side interface). The terms “flash memory device-side interface”, “flash device-side interface” and “flash-side interface” are used herein interchangeably.
These terms (i.e. “host-side interface” and “flash device-side interface”) should not be confused with the terms “host-type interface” and “flash-type interface” which are terminology used herein to differentiate between the two sides of a NAND interface protocol, as this protocol is not symmetric. Furthermore, because it is always the host that initiates the interaction, we note that a given device is said to have a “host-type interface” if the device includes the necessary hardware and/or software for implementing the host side of the NAND interface protocol (i.e. for presenting a NAND host, and initiating the NAND protocol interaction) Similarly, because the flash device never initiates the interaction, we note that a given device is said to have a “flash-type interface” if the device includes the necessary hardware and/or software for implementing the flash side of the NAND protocol (i.e. for presenting a NAND flash device).
Typically, “host-type interfaces” (i.e. those which play the role of the host) are “flash device-side interfaces” (i.e. they interact with flash devices or with hardware emulating a flash device) while “flash device-type interfaces” (i.e. those which play the role of the flash device) are typically “hosts-side interfaces” (i.e. they interact with host devices or with hardware emulating a host device). In this application the term “host device” (or “host” in short) means any device that has processing power and is capable of interfacing with a flash memory device. A host device may be a personal computer, a PDA, a cellular phone, a game console, etc.
Typically, NAND devices are relatively difficult to interface and work with. One reason for that is the relatively complex (compared to NOR devices) protocol for accessing them, as described above. Another difficulty is the existence of errors in the data read from NAND devices, In contrast, NOR devices that can be assumed to always return correct data. This inherent non-reliability of NAND devices requires the use of Error Detection Codes (EDC) and Error Correction Codes (ECC).
Manufacturers of SBC NAND flash devices typically advise users to apply an Error Correction Code capable of correcting 1 bit error in each page of 512 bytes of data. But data sheets of MBC NAND flash devices typically advise applying an ECC capable of correcting 4 bit errors in each page of 512 bytes of data. For pages of size 2048 bytes such as in the case of the NAND devices mentioned above (known as “large block devices”), the suggestion is to apply error correction per each portion of 512 bytes of the page. In this application the term “N-bit ECC” refers to an ECC scheme capable of correcting N bit errors in 512 bytes of data, regardless if the 512 bytes are the size of one page, less than one page, or more than one page.
NAND Controllers
Because of those complexities of NAND devices, it is the common practice to use a “NAND controller” for controlling the use of a NAND device in an electronic system. It is true that it is possible to operate and use a NAND device directly by a host device with no intervening NAND controller, and there are systems that actually operate like this. However, this architecture suffers from many disadvantages. First, the host has to individually manipulate each one of the NAND device's control signals (e.g. CLE or ALE), which is cumbersome and time-consuming for the host. Second, the support of EDC and ECC puts a severe burden on the host—parity bits have to be calculated for each page written, and error detection calculations (and sometimes also error correction calculations) must be performed by the host. All this makes such “no controller” architecture relatively slow and inefficient.
Using a NAND controller significantly simplifies the host's tasks when using the NAND device. The processor interacts with the controller using a protocol that is much more convenient to use—a request for writing a page may be sent as a single command code followed by address and data, instead of having to bother with the complex sequencing of control lines and NAND command codes. The controller then converts the host-controller protocol into the equivalent NAND protocol sequences, while the host is free to do other tasks (or just to wait for the NAND operation to complete, if so desired).
There are several options in the prior art regarding the location where the NAND controller resides within the system. A first approach is shown in FIG. 2. Here the NAND controller 114 is physically located within the host processor 112A of the host device 110A. If the host processor 112A is implemented as a single die, then the controller 114 is incorporated on the same die. This is for example the case in some of the OMAP processors manufactured and sold by Texas Instruments. In a system built using this architecture the host processor typically interacts with the NAND controller using some proprietary protocol, as the interaction is internal to the host processor and there is no benefit in using a standard protocol.
A second prior art approach is shown in FIGS. 3A-3B. Here the NAND controller 116 is a separate physical element, residing between the host processor 112B of the host 110B and the NAND device 120A. This is for example the case in portable USB Flash Drives (UFDs), such as the DiskOnKey manufactured and sold by M-Systems Flash Disk Pioneers, where there is a NAND controller 116 packaged inside the UFD and interacting using a device side NAND interface 124 with the NAND device 120A on one side and with the host processor 112B on the other side (using a host side USB interface 122 which uses the USB protocol). In a system built using this architecture the host processor typically interacts with the NAND controller using a standard protocol such as USB or ATA, as the interaction is external to the processor and it is more convenient to use standard protocols that are already supported by the processor for other purposes.
Note that according to the terminology previously defined, NAND interface 124 is a “flash memory device side NAND interface” (i.e. adapted to interact with NAND flash device 120A) but at the same time NAND interface 124 is also a host-type NAND interface (i.e. adapted to initiate the NAND protocol interaction).
A third prior art approach is shown in FIG. 4. Here the NAND controller 118 is physically located within the NAND device 120B. The flash device and the controller may even be implemented on the same die. This is for example the case in some of the MDOC storages devices manufactured and sold by M-Systems Flash Disk Pioneers and in the OneNAND devices manufactured and sold by Samsung Electronics. In a system built using this architecture the host processor 112B typically interacts with the NAND controller using either a standard protocol such as USB or a semi-standard protocol as is the case in the MDOC and OneNAND examples mentioned above.
We can deduce from the above that a prior art stand-alone NAND controller (that is not integrated with neither the NAND device nor the host processor) will typically have some standard interface on its host side, and a NAND interface on its flash memory device side (for example, see FIG. 3B). Indeed one can find in the market NAND controllers exporting many interface types—USB, SD (SecureDigital), MMC (MultiMediaCard), and more. However, one cannot currently find a stand-alone NAND controller that exports NAND interface to the host. Indeed, this is reasonable to expect—a host processor that does not have built-in NAND support and requires an external controller for that purpose, typically does not have a NAND interface and cannot directly connect to a device exporting a NAND interface and therefore has no use of a controller with host-side NAND interface. On the other hand, a host processor that has built-in NAND support typically also includes a built-in NAND controller and can connect directly to a NAND device, and therefore has no need for an external NAND controller.
The prior art described above leaves one problem unsolved. Assume that there is a host processor incorporating a built-in NAND controller and a NAND interface as in FIG. 2. The built-in controller is designed to work with NAND devices of a certain level of reliability. This is so because a NAND controller provides a certain level of error detection and correction, and therefore cannot support NAND devices with lower reliability. For example, a NAND controller having a 1-bit ECC can work with SBC NAND devices that are specified by their manufacturers to require only this level of error correction. Such controller cannot work with two-bit-per-cell MBC NAND devices because they require 4-bit ECC, and therefore some data might not be read correctly into the processor. Similarly, a NAND controller providing 4-bit ECC can work with current two-bit-per-cell MBC NAND, but will not work with next generation MBC NAND devices that will most probably require a higher level of ECC capability.
This is so because future MBC NAND devices are expected to be less reliable than current MBC devices and to require a much stronger ECC capability. The reasons for the reduced reliability and increased error rate are twofold:
a. The process used for manufacturing NAND devices is continuously being improved to yield smaller memory cells. While a few years ago NAND devices used 0.4 micron process, currently they use 90 nm and 70 nm technology, and this shrinking trend is expected to continue. With shrinking dimensions of the memory cells comes lower reliability, as the small dimensions make the cells more sensitive to physical effects and phenomena that previously were not important.
b. When MBC cells with more than two bits per cell will become commercially available, they will necessarily be much less reliable than SBC cells and two-bit-per-cell MBC cells. The larger number of states that have to be represented by the cell's threshold voltage imply that the margins between states are smaller and even smaller disturbances and drifts result in incorrect reading of data. This effect could already be witnessed in the comparison between SLC and two-bit-per-cell MBC, where the ECC requirements increased from 1-bit ECC to 4-bit ECC.
Returning now to the host processor 112A with the built-in NAND controller 114, suppose the controller 114 supports only 1-bit ECC. Then this processor might not be able to use MBC NAND even though this is highly desirable because of the MBC NAND lower cost. If the MBC NAND is connected to the NAND interface of the built-in controller of the processor, which might be the only way to connect it to the processor, then the MBC NAND generates too many errors for the limited-capability ECC of the built-in controller to correct.
Similarly, if the built-in controller supports 4-bit ECC, it can use both SLC and two-bit-per-cell MBC NAND. But when NAND devices with lower reliability appear in the market, the processor is not able to benefit from their lower price because its built-in controller is not able to provide the required level of error correction.
Therefore we see that the state of the prior art does not provide a good solution to the problem of benefiting from the cost advantage of a new NAND device, while using a host processor incorporating a built-in NAND controller designed to support a previous generation of NAND devices.
There is an ongoing need for devices and methods that provide compatibility between a host device having an onboard NAND controller and successive generations of NAND flash memory devices.